The present invention relates generally to a semiconductor memory device, and more precisely to a sense amplifier control circuit controlling a sense amplifier.
In general, a semiconductor memory device includes the sense amplifier, which senses and amplifies the charge sharing in bit line of the semiconductor memory device by an active signal. In order to improve the amplifying speed of the sense amplifier, the memory device can use an overdriving method that drives the sense amplifier with an overdrive voltage, e.g., a boost voltage VPP, higher than a core voltage VCORE which is a cell capacitance potential at the beginning of amplification. Referring to FIG. 1, the sense amplifier control circuit comprises a pull-up control signal generating unit 10, which receives an active signal ACT and generates an overdrive control signal SAP1 and a pull-up control signal SAP2, and a pull-down control signal generating unit 12, which receives the active signal ACT and generates a pull-down control signal SAN.
Herein, the pull-up control signal generating unit 10 combines the active signal ACT with a delay signal D1 obtained by delaying the active signal ACT to generate the overdrive control signal SAP1 and the pull-up control signal SAP2 which are sequentially enabled. That is, the pull-up control signal SAP2 is enabled at a time point when the overdrive control signal SAP1 is disabled.
Referring to FIG. 2, the delay circuit 14 includes a plurality of delay chains DC1 to DC4 which are connected in series.
Each of delay chains DC1 to DC4 delays the input signal by a prescribed time tD and outputs it. Subsequently, if the delay chains DC1 to DC4 are connected in series, the output signal is a signal which delays the input signal for a time t4D obtained by multiplying the time tD delayed via each delay chain DC1 to DC4 by the number of the delay chains (herein, 4).
That is, the delay circuit 14 outputs the delay signal D1 obtained by delaying the active signal ACT by the prescribed time 4tD, via each delay chain DC1 to DC4.
Meanwhile, the delay time tD delayed by each delay chain DC1 to DC4 depends on a potential of the power supply voltage VDD. This is because the delay cell 16 (DU: Delay Unit) included in each delay chain DC1 to DC4 is influenced by the potential of the power supply voltage VDD.
As shown in FIG. 2, the delay cell 16 can be composed of a plurality of inverters IV1 to IV4 connected in series, in which the inverters IV1 to IV4 are characterized in having an operation velocity varied in accordance with the potential of the power supply voltage VDD. In other words, the delay time tD of the input signal IN depends on the potential of the power supply voltage VDD.
That is, if the potential of the power supply voltage VDD increased, the operation velocity of each inverter IV1 to IV4 also increases, and consequently the delay time of the input signal IN is reduced. On the other hand, if the potential of the power supply voltage VDD is decreased, the operation velocity of each of the inverters IV1 to IV4 is also decreased, and therefore the delay time of the input signal IN is increased.
The operation of the sense amplifier control circuit shown in FIG. 1 will be explained in reference to FIG. 3. If the active signal ACT is enabled, the pull-up control signal generating unit 10 receives the active signal ACT, which is delayed by the prescribed time D by the delay circuit and the delay circuit 14 outputs the delay signal D1. The pull-up control signal generating unit 10 NAND-combines the active signal ACT with a signal obtained by inverting the delay signal D1 to generate a signal D2. The pull-up control signal generating unit 10 generates an overdrive control signal SAP1 by inverting the signal D2. Further, the pull-up control signal generating unit 10 generates the pull-up control signal SAP2 by NOR-combining the inverted active signal D3 with the overdrive control signal SAP1. The pull-up control signal SAP2 is enabled at a time point when the overdrive control signal SAP1 is disabled.
The pull-down control signal generating unit 12 generates the pull-down control signal SAN which is enabled in synchronization with an enable time point of the overdrive control signal SAP1 and the pull-down control signal SAN is disabled in synchronization with a disable time point of the pull-up control signal SAP2, if the active signal ACT is enabled.
An enable pulse width PW1 of the overdrive control signal SAP1 is determined by the delay time D of the delay signal D1 delayed by the delay circuit 14 as illustrated in FIG. 1.
Referring to FIG. 4, when the sense amplifier control signals SAP1, SAP2, and SAN are given as shown in FIG. 3, an operation of the sense amplifier will be described.
When the cell transistor permits charge sharing with bit lines by driving word lines selected by the active signal, the sense amplifier amplifies a potential of the bit line (for example, BL) rapidly up to a level of the core voltage VCORE if the overdrive voltage VPP is applied by the overdrive control signal SAP1.
And then, the sense amplifier remains the potential of the bit line BL at the level of the core voltage VCORE if the core voltage VCORE is applied by the pull-up control signal SAP2 enabled sequentially after the overdrive control signal SAP1 is disabled.
Further, if a ground voltage VSS is applied by the pull-down control signal SAN, the sense amplifier amplifies the potential of the bit line (for example, BLB) to the level of the ground voltage VSS.
As such, the sense amplifier performs the overdrive operation during a section PW1 when the overdrive control signal SAP1 is enabled, in which the enable pulse section PW1 of the overdrive control signal SAP1 may be designed in response to the operation voltage. That is, the semiconductor memory device may be designed with the enable pulse width PW1 of the overdrive control signal SAP1 corresponding to a case that the operational voltage is, for example, 1.8V.
The potential of the power supply voltage VDD can be varied from 2.1V to 1.5V, but the enable pulse width PW1 of the overdrive control signal SAP1 must be controlled in response to changes of the power supply voltage VDD. The sense amplifier control circuit according to prior art cannot randomly control the enable pulse width PW1 of the overdrive control signal SAP1 in response to changes of the power supply voltage VDD.
As a result, if the power supply voltage VDD is increased, the potential of the bit line BL is unnecessarily above the level of the core voltage VCORE during performance of the overdrive operation, which results in increasing current consumption.
Further, if the power supply voltage VDD is lowered, the potential of the power supply voltage VDD is unnecessarily below the level of the core voltage VCORE during performance of the overdrive operation, as a result it is difficult to perform the normal operation.